Design Verification Engineer

We are seeking a seasoned Design Verification Engineer with a strong background
in building testbenches and writing test sequences for complex IPs. The ideal
candidate will play a key role in shaping our technology portfolio, bringing expertise
and creativity to our solutions
Responsibilities :
Create test plans for highly configurable IPs meant to provide interconnectivity
between components across an SoC, chiplet, or multi-chiplet systems
Write UVM/SystemVerilog code to implement the test plan, checkers, and
scoreboards
Collaborate with software teams to define and implement configurable test
benches
Work with design teams test plans, failure debug, coverage, etc.
Qualifications and Preferred Skills
BS, MS in Electrical Engineering,
Computer Engineering or Computer Science
8 years and current hands-on experience in block-level/IP-level/SoC-level
verification
Proficiency in Verilog, SystemVerilog
Familiarity with industry-standard EDA tools for simulation and debug
Deep experience with UVM-based test benches
Experience with modern programming languages like Python
Knowledge of Arm AMBA protocols such as AXI, APB, and AHB
Understanding of Arm CHI protocol is a plus
Experience on working with IPs for caches, cache coherency, memory
subsystems, interconnects and NoCs
Experience with formal verification techniques, emulation platforms is a plus
Excellent problem-solving skills and attention to detail
Strong communication and collaboration skills
LEVEL OF EXPERTISE
Verilog - 8 years
Universal Verification Methodology - UVM - 8 years
Python - 6 years
EDA (Electronic Design Automation) - 6 years