MTS RTL Design Engineer

Position Summary:

We are seeking a highly motivated and technically skilled MTS RTL Design Engineer to join our silicon design team. As an RTL (Register Transfer Level) Design Engineer at the Member of Technical Staff level, you will be responsible for architecting, designing, and optimizing digital logic blocks for high-performance, low-power System-on-Chip (SoC) solutions. You will work closely with microarchitecture, verification, synthesis, and physical design teams to ensure functional correctness, performance goals, timing closure, and design quality. This is a hands-on technical role where deep understanding of digital design principles, hardware description languages, and SoC architecture is essential. The ideal candidate will have strong RTL design expertise using Verilog/SystemVerilog, solid experience with design tools and flows, and a collaborative mindset.

Key Responsibilities:

1. RTL Design and Development:

• Design and develop synthesizable RTL code using Verilog or SystemVerilog for complex digital blocks and subsystems.
• Translate high-level architecture specifications into microarchitecture and RTL implementations.
• Ensure the RTL is optimized for area, power, and performance (PPA), adhering to design constraints.
• Use RTL linting, CDC (Clock Domain Crossing) checks, and formal tools to ensure design robustness.

2. Microarchitecture Definition:

• Collaborate with architects to define and refine the microarchitecture of assigned design blocks.
• Document microarchitectural specifications, design assumptions, and interface requirements.
• Break down large subsystems into well-defined, reusable RTL components.

3. Design Integration and Interface Management:

• Integrate IP blocks, third-party cores, and internal modules into larger subsystems.
• Develop and manage interface logic for protocols like AMBA (AXI/AHB/APB), PCIe, USB, or custom buses.
• Work with verification teams to ensure clear design intent and provide necessary hooks and debug support.

4. Design Quality and Verification Support:

• Collaborate with verification engineers to define test plans and provide functional coverage goals.
• Assist in debug and root-cause analysis of functional bugs during simulation or emulation.
• Use assertions and formal verification techniques to improve design reliability.

5. Synthesis and Timing Closure:

• Prepare RTL for synthesis using tools such as Design Compiler, Genus, or equivalent.
• Analyze synthesis results, resolve timing issues, and iterate on RTL for optimization.
• Ensure that the RTL meets timing, power, and area constraints post-synthesis.

6. Documentation and Reviews:

• Maintain up-to-date design documentation including block diagrams, specifications, and design notes.
• Participate in design reviews and provide constructive feedback to peers.
• Follow internal design processes, review checklists, and signoff criteria.

Job Profile : MTS RTL Design Engineer
Industry : Core-Technical, multimedia