Digital Design Verification Intern

Hi Aspirants.. Grab the below exiting Free Un-Paid Internship opportunity at Relicuus Technologies & Role: Digital Design Verification Intern Duration: 6months
Benefits of Internship: 1) Free Hands-on training on System Verilog, UVM for design verification from Experienced mentors 2) Free Hands-on training on industry required Onchip, Offchip bus protocols 3) Hands-on real time projects with industry experienced resources 4) Real time work experience, Industry standard skillset 5) Mock Interviews, Placement support after internship completion 6) Internship completion certificate & Requirements: 1) MTech(PG) passout in ECE/EEE domain with 70% above aggregate. 2) Strong in Digital circuits design and implementation using Verilog 3) Knowledge on System Verilog and UVM is advantageous. & 4) C, C , Python, Perl programming&
Mode: Offline, Work from office only
Criteria for selection: 1) Offline Written test and Face2face Interview.
Note: No Stipend/Salary will be paid during Internship Tenure & Apply now: Share your resume to us Date for application: 30th May 2025 Shortlisted candidates will receive interview call letters.

Job Profile : Digital Design Verification Intern
Industry : Core-Technical