RTL Design Verification Intern

Hi Aspirants.. Grab the below exiting Free Un-Paid Internship opportunity&
Role: RTL Design Verification Intern Benefits: 1) Free Hands-on training on System Verilog, UVM, Industry required protocols. 2) Get to work on real time projects with Industry experienced professionals. 3) Realtime work experience and upgrade skillset to match industry standards. 4) Gives more job opportunities post internship. 5) Mock Interviews, Placement support post internship. 6) Internship Completion Certificate.
Requirements: 1) MTech(PG) passout in ECE/EEE domain with 70% above aggregate. 2) Strong in Digital circuits design and implementation using Verilog 3) Knowledge on System Verilog and UVM is advantageous. 4) C, C , Perl , Python & Criteria for selection: 1) Offline Written test and Face2face Interview. & Internship Duration: 6months
Mode of work: Offline, Work from office only Note: No Stipend/salary will be paid during internship tenure.
Apply now: Share your resume to us Date for application:& before 30th May 2025 Shortlisted candidates will get the interview call letter.

Job Profile : RTL Design Verification Intern
Industry : Core-Technical